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Appendix D - Ethernet Timing Table

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HDL-64E S2 User’s Manual

HDL-64E S2 Ethernet Timing Table Overview

The HDL-64E S2 Ethernet Timing Table is designed to answer the question of how much time

elapses between the actual capturing of a distance point and when that point is output from the

device. By registering the event of the Ethernet data capture, HDL-64E S2 users can then

trace back in time the exact point in time at which any particular distance point was captured

by the HDL-64E S2.

In the HDL-64E S2, the upper block and lower block collect distance points simultaneously, with

each block issuing single laser pulses at a time. That is, each upper block laser fires in

sequence and in unison to a corresponding laser from the lower block. For example, laser 32

fires simultaneously with laser 0, laser 33 fires with laser 1, and so on. Unlike the HDL-64E,

which issued three upper block returns for every lower block return, the HDL-64E S2 has an

equal number of upper and lower block returns. This is why when interpreting the delay table

each sequential pair of data blocks will represent the upper and lower block respectively,

and each upper and lower block pair of data blocks in the Ethernet packet will have the same

delay values.

Ethernet packets are assembled until the entire 1200 bytes have been collected, representing

six upper block sequences and six lower block sequences. The packet is then transmitted via

a UDP packet over Ethernet, starting from the last byte acquired. See a sample of the packet

layout on page 20.

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Velodyne HD HDL-64E S2.1 Bedienungsanleitung Seite 21